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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct597 8-bit shift register with input flip-flops for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 features 8-bit parallel storage register inputs shift register has direct overriding load and clear output capability: standard i cc category: msi general description the 74hc/hct597 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct597 consist each of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. both the storage register and the shift register have positive edge-triggered clocks. the shift register also has direct load (from storage) and clear inputs. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay c l = 15 pf; v cc =5v sh cp to q 17 20 ns st cp to q 25 29 ns pl to q 21 26 ns f max maximum clock frequency sh cp 96 83 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 29 32 pf
december 1990 3 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 pin description pin no. symbol name and function 8 gnd ground (0 v) 9 q serial data output 10 mr asynchronous reset input (active low) 11 sh cp shift clock input (low-to-high, edge-triggered) 12 st cp storage clock input (low-to-high, edge-triggered) 13 pl parallel load input (active low) 14 d s serial data input 15, 1, 2, 3, 4, 5, 6, 7 d 0 to d 7 parallel data inputs 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 function table notes 1. h = high voltage level l = low voltage level x = dont care - = low-to-high cp transition st cp sh cp pl mr function - x x x data loaded to input latches - x l h data loaded from inputs to shift register no clock edge x l h data transferred from input ?ip-?ops to shift register x x l l invalid logic, state of shift register indeterminate when signals removed x x h l shift register cleared x - h h shift register clocked q n =q n - 1 , q 0 =d s fig.4 functional diagram.
december 1990 5 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 fig.5 logic diagram.
december 1990 6 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 fig.6 timing diagram.
december 1990 7 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sh cp to q 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.7 t phl propagation delay mr to q 58 21 17 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay st cp to q 80 29 23 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 fig.7 t phl / t plh propagation delay pl to q 69 25 20 215 43 37 270 54 46 325 65 55 ns 2.0 4.5 6.0 fig.9 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.9 t w st cp pulse width high or low 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7 t w sh cp pulse width high or low 80 16 14 14 5 4 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.7 t w mr pulse width low 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.8 t w pl pulse width low 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.9 t rem removal time mr to sh cp 60 12 10 - 3 - 1 - 1 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.10 t su set-up time d n to st cp 60 12 10 8 3 2 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.11
december 1990 8 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 t su set-up time d s to sh cp 60 12 10 11 4 3 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.11 t su set-up time pl to sh cp 60 12 10 11 4 3 75 15 13 90 18 15 ns 2.0 4.5 6.0 fig.12 t h hold time d n to st cp 5 5 5 - 3 - 1 - 1 5 5 5 5 5 5 ns 2.0 4.5 6.0 fig.11 t h hold time pl, d s to sh cp 5 5 5 - 6 - 2 - 2 5 5 5 5 5 5 ns 2.0 4.5 6.0 fig.11 f max maximum pulse frequency sh cp 6.0 30 35 29 87 104 4.8 24 28 4.0 20 24 mhz 2.0 4.5 6.0 fig.7 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max.
december 1990 9 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient d s d n pl, mr st cp , sh cp 0.25 0.30 1.50 1.50
december 1990 10 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 ac waveforms for 74hct gnd = 0 v; t r =t f = 6 ns; c l =50pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms +25 - 40 to +85 - 40 to +125 min. typ. max. min. max. min. max. t phl / t plh propagation delay sh cp to q 23 40 50 60 ns 4.5 fig.7 t phl propagation delay mr to q 28 49 61 74 ns 4.5 fig.8 t phl / t plh propagation delay st cp to q 33 57 71 86 ns 4.5 fig.7 t phl / t plh propagation delay pl to q 30 52 65 78 ns 4.5 fig.9 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.9 t w sh cp pulse width high or low 16 7 20 24 ns 4.5 fig.7 t w st cp pulse width high or low 16 6 20 24 ns 4.5 fig.7 t w mr pulse width low 25 14 31 38 ns 4.5 fig.8 t w pl pulse width low 20 10 25 30 ns 4.5 fig.9 t rem removal time mr to sh cp 12 - 2 15 18 ns 4.5 fig.10 t su set-up time d n to st cp 12 5 15 18 ns 4.5 fig.11 t su set-up time d s to sh cp 12 2 15 18 ns 4.5 fig.11 t su set-up time pl to sh cp 12 4 15 18 ns 4.5 fig.12 t h hold time d n to st cp 5 - 1 5 5 ns 4.5 fig.11 t h hold time pl, d s to sh cp 5 - 2 5 5 ns 4.5 fig.11 f max maximum pulse frequency sh cp 30 75 24 20 mhz 4.5 fig.7
december 1990 11 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 ac waveforms fig.7 waveforms showing the sh cp and st cp inputs to q output propagation delays, the sh cp and st cp pulse widths and maximum clock pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.8 waveforms showing the mr input to q output propagation delays and the mr pulse width. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.9 waveforms showing the pl input to q output propagation delays, pl pulse width and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. fig.10 waveforms showing the mr input to sh cp , st cp removal times. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.
december 1990 12 philips semiconductors product speci?cation 8-bit shift register with input ?ip-?ops 74hc/hct597 fig.11 waveforms showing hold and set-up times for d s , d n inputs to sh cp , st cp inputs. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v. package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.12 waveforms showing set-up times for pl input to sh cp input. (1) hc : v m = 50%; v i = gnd to v cc . hct : v m = 1.3 v; v i = gnd to 3 v.

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